1. Field of the Invention
The present invention relates to a rail-to-rail differential input terminal for an operational amplifier, and more particularly, to an improved transconductance control circuit for a rail-to-rail differential input terminal.
2. Description of the Background Art
As a VLSI (very large scaled integrated) circuit prefers a low supply voltage (less than 3.3V), a complementary CMOS circuit has significantly decreased its operational range. One of the analog circuits most effected by the decreased supply voltage is an input terminal 10 connected to an operational amplifier 20 as shown in FIG. 1. The input terminal 10 generally includes a single differential input pair having a common mode input range which is half the entire supply voltage range.
Such a single differential input pair are confined to either side of the supply rail and accordingly are inappropriate to a low voltage (3.3V) application. In application fields of low voltages (less than 3.3V), the input terminal 10 is implemented as an inter-complementary differential input pair so as to extend a common mode input range to an entire RTR.
FIG. 2 shows a schematic construction of a conventional CMOS RTR differential input terminal 100 including an inter-complementary differential input pair, wherein NMOS transistor pair NM1, NM2 and PMOS transistor pair PM1, PM2 are parallel connected.
A first differential input Vin1 is applied to respective gates of the PMOS transistor PM1 and the NMOS transistor NM1. A second differential input VIN2 is applied to respective gates of the PMOS transistor PM2 and the NMOS transistor NM2. At this time, the first and second differential inputs Vin1, Vin2 form a common mode. Also, bias current Ip is induced from supply voltage VDD terminal to the PMOS transistor pair PM1, PM2, and a bias current In is induced from respective sources of the NMOS transistor pair NM1, NM2 to ground.
The operation of the thusly constituted conventional differential input terminal 100 will now be described.
Depending upon a common mode voltage V.sub.CM of the first and second differential inputs Vin1, Vin2, the RTR differential input terminal 100 is provided with three operational types.
That is, when the common mode voltage V.sub.CM is close to Vss, only the PMOS transistors PM1, PM2 are driven, when the common mode voltage V.sub.CM exists between Vdd and Vss the PMOS transistors PM1, PM2 and NMOS transistors NM1, NM2 are all operated, and when the common mode voltage V.sub.CM is close to Vdd also the NMOS transistors NM1, NM2 are operated. Here, the NMOS transistor pair and the NMOS transistor pair are matching with each other.
At this time, an important parameter in the above operation is a transconductance gm, since a unity gain frequency of the operational amplifier 20 is proportional to the transconductance of the input terminal 10. Namely, a constant transconductance secures the unity gain frequency of the operational amplifier 20 within the entire common mode input range.
In FIG. 2, a transconductance gmp of the PMOS transistors and a transconductance gmn of the NMOS transistors have characteristics as shown in FIG. 4, in accordance with voltage drop of gate-supply voltages Vgs of a PMOS transistor PM3 and an NMOS transistor NM3. Also, the total transconductance gmt is implemented by adding gmp and gmn.
As shown in FIG. 4, the total transconductance gmt is highly variable in the common mode input range V.sub.CM. Therefore, the conventional RTR differential input terminal 100 enables the common mode input range to extend to the entire supply rail but the size and variation of the total transconductance gmt is disadvantageously large, thereby deteriorating frequency characteristics of the operational amplifier 20.
Specifically, as shown in FIG. 4, the total transconductance gmt in the common mode input range shows about 100% in variation, that is, from minimal 8 to maximal. As a result, in accordance with the large variation of the transconductance gmt, the operational amplifier 20 does not obtain a single gain frequency, whereby the frequency compensation of the operational amplifier 20 becomes difficult.
So, a transconductance control circuit is employed at the RTR input terminal so as to decrease variation of the total transconductance gmt.
FIG. 3 shows a current detection circuit 102 as a portion of a transconductance control circuit.
As shown therein, PMOS transistors PM4.about.PM7 are large size transistors (W=2.mu.m, L=500.mu.m) identical to the NMOS transistors NM1, NM2 provided in the RTR differential input terminal 100, wherein PMOS transistors PM6, PM7 form current mirror.
As the input voltage Vin increases, the bias current Ip induced to the PMOS transistor PM3 becomes equal to the current at the PMOS transistor PM6. current at the PMOS transistor PM6 is copied into the PMOS transistor PM7 in accordance with the current mirror operation of the PMOS transistors PM6, PM7, thereby detecting the bias current Ip.
The detected bias current is applied to a bias circuit (not shown) so that the current In which flows through an n-type MOS transistor pair NM1, NM2 as shown in FIG. 2 is controlled.
However, the conventional current detection circuit should provide large size PMOS transistors PM6, PM7 identical to the NMOS transistor pair PM1, PM2 so as to detect the bias current Ip which flows through the PMOS transistor pair PM1, PM2, thereby disadvantageously increasing chip size in implementation of the current detection circuit.
Further, the conventional current detection circuit has two DC paths which lead from Vdd to Vss, thereby increasing power consumption.